1. Field of the Invention
The present invention relates generally to a semiconductor device and, more specifically, to a semiconductor device which can suppress the operation of a parasitic transistor as developed in an insulated gate bipolar transistor (hereinafter referred to as an IGBT) and in a dual-diffusion MOS field effect transistor (DMOS FET).
2. Description of the Related Art
Generally, an IGBT is of such a type as to have the low saturation voltage characteristic of a bipolar transistor and high-speed switching and high input impedance characteristics of a MOS FET.
The IGBT is used, as a switching device, in various associated circuits in view of less loss at the time of power conversion and less electric power for use in driving. The MOS FET has the same advantages as the IGBT and has been adopted in various circuits for an application principally required for high-speed switching.
That type of transistor as set out above is liable to produce an unwanted latch-up phenomenon resulting from the operation of the parasitic transistor as generally known in the art. The latch-up occurs upon the flow of a large current, such as the short-circuiting of a load, causing the device to be placed in an uncontrollable state. Unless the device is rendered nonconductive, abnormal current continues to flow across a power source and ground and, sometimes, the device is caused to be destroyed due to a temperature rise, etc. Further a DMOS FET, upon a rapid change in a voltage applied thereto, may be accompanied by the ON operation of a parasitic transistor and cause a breakage.
In the IGBT and MOS FET, however, a parasitic transistor is unavoidably involved due to their structural nature and the prevention of the ON operation of such a parasitic transistor is a great task to be solved.
Attempts have been made to prevent the turning on of a possible parasitic transistor by the adoption of a specific arrangement. Of these, the most common attempt is to lower the resistance R.sub.B of a base region so as to prevent a rise in a forward voltage on a base/emitter junction of a parasitic NPN transistor in the case of an N channel IGBT and MOS FET.
The lowering of the resistor R.sub.B is achieved, for example, (1) in a highly concentrated base region, (2) in a deep base region, (3) in emitter regions divided in the lateral width direction and (4) in an N type emitter region partly cut in the lateral width direction.
If these are adopted in the device, it is possible to control the conduction of the parasitic transistor, but the ON voltage of the device is raised and, at the same time, the mutual conductance is lowered due to an increase (a second case) or a decrease (a third case) in the channel region involved.
Thus the lowering of the resistance R.sub.B thus conventionally attempted results in an increase in power loss and a rise in gate drive voltage.